The present invention has utility in applications requiring the conversion of an analog signal into a digital signal, for example, for computer sensing of analog information in an automotive control system. To further illustrate, in an automotive engine control system, a microcomputer requires analog signal information from various sensing devices which must be converted into digital signal information before it can be processed by the microcomputer. Examples of such analog signal information are the outputs of sensors for manifold pressure, oxygen, rotational speed, operator input, battery voltage, etc.
In a typical automotive application, many different analog signals need to be converted. Some analog signals need to be measured frequently, such as rotational speed, and other analog signals must only be measured occasionally. Still other analog signals need to be measured only when a defect or error condition has been detected within the automotive system. In addition, some analog signals which are part of the same automotive system, such as the anti-lock braking system, must be measured at points very close together in time.
Prior art microcomputers used a software program, executed by the central processing unit, in order to determine which analog signals were to be converted by an A/D (analog to digital) converter. The A/D conversions which were required to be measured at points close together in time were generally placed in the same software subroutine. It was usually necessary to place an upper limit on the maximum interrupt latency of the system. A maximum interrupt latency ensured that the conversions within the same subroutine all occurred within a known maximum period of time. However, as automative systems increased in complexity, the need for more conversions in a subroutine required an increase in the maximum interrupt latency; while the need to take measurements closer together in time required a decrease in the maximum interrupt latency.
Thus there is a significant need to provide an A/D converter system in which interrupt latency is not a limiting factor.